Document CN101871908B discloses a commonly used system consisting of a front-end element, i.e. one that aggregates an analogue (e.g. voltage) signal, containing information, connected to an external ADC discretization system that processes analogue information into digital one. The ADC system then sends the digital signal via a data bus to a FPGA type computation unit, which processes the data and sends it to the main computation unit MCU. The document also discloses a reverse process, wherein data is sent from the MCU to a high-speed FPGA computation unit, which processes and sends it to a DAC system, which processes it into an analogue (e.g. voltage) signal and sends it to the front-end. The described solution has a separate DAC and ADC system. This solution is prone to interference that occurs downstream and upstream the ADC or DAC systems, so that it is extremely difficult to detect and filter out. Another disadvantage is the necessity to transfer data between the separate DAC and ADC, FPGA and MCU processing systems using external buses. The available peripheral DAC and ADC systems are characterized by low data processing capabilities, so that a microcontroller of this type is not applicable in the processing and analysis of high speed signals.
Document CN105119618B describes an improved solution relative to a prior document consisting in the integration of a computation unit and ADC and DAC systems within one computation unit MCU. The disclosed solution solves the problem of interference occurring during the operation of peripheral ADC and DAC systems at the cost of a significant reduction of the processor's computing power and a decelerated operation of the entire system. The computing power is divided among individual elements, which means that if large amounts of data are involved, ADC and DAC systems process large amounts of data and the computation unit is unable to timely process and send it.
There are solutions available on the market offering computation units equipped with efficient and high speed DAC (Digital to Analogue Conversion) and ADC systems for work in the “offline” system, e.g. LPC4370 processor from the company NXP or STM32L496XX from the company STMicroelectronics. The processor works in a system with high speed memory in cycles: first, the processor receives a high speed analogue, e.g. voltage, signal. The signal gets directly to the high-speed (e.g. 80 million samples per second) ADC converter which generates a large amount of data in a very short time. The computation unit does not have sufficient capacity to process it in real time (online mode). Therefore, data in digital form is directed to the high speed memory via a parallel bus. Once the memory is full, data reception stops (offline mode), and the processor retrieves data from memory and processes it at a lower speed than the one at which the data was generated by the ADC system. This solution is not applicable in the analysis of continuous processes, as the time required for the data to be processed exceeds many times the duration of the signal received. Therefore, a system of this kind can only work in processes that require periodic control of a section of the signal.